The present invention relates generally to the field of buses utilized to facilitate communication between electronic devices, as well as buses implemented within integrated circuits. The present invention is more particularly related to methods and apparatuses for providing a programmable data bus.
Buses interconnect logic devices to allow the devices to communicate with each other. Typically, buses include an address bus and a data bus. In order to communicate, an address is provided on the address bus indicating which piece of information is being sent or retrieved. The corresponding piece of data is also provided on the data bus. Methods and techniques for reading and writing information to and from logic devices are well known in the art and will not be discussed in greater detail.
Typically, buses have been used to inter connect logic devices or integrated circuits in one of two manners. In one instance data flow is serial in nature. That is, data is passed from one integrated circuit to another integrated circuit through a bus and then passed on to a subsequent integrated circuit through another bus, referring to FIG. 1A. FIG. 1A is a block diagram of a prior art method of utilizing buses. Chip layout 10 may include a direct memory access (DMA) chip 12, a mixer 14 and a coder/decoder (CODEC) 16. The integrated circuits are coupled together through buses 13 and 15. Buses 13 and 15 generally include an address bus and a data bus.
Data from DMA 12 may be relayed to mixer 14 through bus 13 in order to allow mixer 14 to perform operations on the data passed along from DMA 12. In this example, the data passed to mixer 14 may then be passed on to CODEC 16 for further processing. Another bus 15 is then required to pass along the data from mixer 14 to CODEC 16.
Utilization of buses in a serial format, as depicted in FIG. 1A, has several limitations. A primary limitation of a serial configuration is that the buses may only be utilized for one purpose. As in FIG. 1A, bus 13 can only be used to transfer information from DMA 12 to mixer 14, and bus 15 may only be utilized to transfer information from mixer 14 to CODEC 16. Often times, routing of buses on circuit boards and/or integrated circuits require a large amount of space, generally a scarce commodity. Thus, having to have multiple buses in order to accommodate the data flow from DMA 12 to mixer 14 and then to CODEC 16 is non-optimal at best and prohibitively expensive in terms of board real estate.
Another problem with a serial bus configuration is synchronization. The data flow from DMA 12 to mixer 14 must be synchronized to ensure that mixer 14 receives data at an appropriate rate. Similarly, the data flow from mixer 14 to CODEC 16 must also be synchronized. If the integrated circuits 12, 14 and 16 are operating at different clock rates provisions must be made to ensure that the data rates over buses 13 and 15 accommodate the different clock rates of the integrated circuits. Furthermore, a final output of CODEC 16 is consequently delayed by a latency time period which is equivalent to the amount of processing time required by DMA 12, mixer 14, CODEC 16 and the time to transfer the data over buses 13 and 15.
The prior art bus configuration of FIG. 1A is a simplistic one. Now referring to FIGS. 1B and 1C, more complicated examples of serial bus configurations are depicted. FIG. 1B depicts a prior art configuration 20. The configuration includes a number of processing blocks or integrated circuits DMA 22, mixer 23, digital signal processor (DSP) 25, sample rate converter 27, mixer 29, and CODEC 33. Intercoupling the processing blocks are buses 24, 26, 28, 31, 32.
DMA 22 may wish to pass on information through bus 24 to either mixer 23 and sample rate converter 27. DMA 22 may then address the appropriate processing blocks in order to send data to either mixer 23 or sample rate converter 27 along bus 24. Accordingly, bus 24 would include an address bus and a data bus.
After mixer 23 or sample rate converter 27 have performed the necessary operations on the data provided by DMA 22 the data may be passed along to mixer 29 along bus 28 and bus 31, respectively. Since buses 28 and 31 only convey data from one source to one destination they may only include a data bus with appropriate control lines.
In order for mixer 29 to accomplish its necessary functions it may need to utilize a DSP 25. Mixer 29 communicates with DSP 25 over bus 26. Bus 26 typically includes an address bus and a data bus since a DSP may include a number of different address locations to be written to or read from. Finally the output of mixer 29 may them be sent to CODEC 33 across bus 32, which may only include a data bus and control lines.
As can be seen in FIG. 1B a large number of buses are required to transfer the appropriate data from DMA 22 to CODEC 33. All total, five buses are required in order to intercouple six processing blocks or integrated circuits. Only in one case is a bus capable of transferring information from more than one block to another, i.e., bus 24. However, bus 24 is still limited to unidirectional data flow. The other buses simply transfer data from one processing block to another, without being able to perform any other function. Furthermore, the buses are specifically synchronized to the processing blocks to which they are connected. At any one time buses 24, 26, 28, 31, and 32 may have been operating at different frequencies.
FIG. 1C is a prior art configuration 40 of another serial data flow configuration. Configuration 40 includes DMA 42, DMA 45, mixer 43, sample rate converter 48 and CODEC 49. The processing blocks are connected together by buses 50 through 53. In this particular configuration, data flows in a parallel path from DMA 42 to CODEC 49 and DMA 45 to CODEC 49.
Data from DMA 42 is passed along bus 50 to mixer 43 and then along bus 52 to CODEC 49. Data from DMA 45 is passed along bus 51 to sample rate converter 48 and bus 53 to CODEC 49. Again, the same problems exist in this configuration as in the configurations depicted in FIGS. 1A and 1B. The buses 50-53 may only be utilized to transfer data from one processing block to another, without modification or alterations to serve any other function. Also the buses 50-53 may be operating at different speeds. Thus, the output of CODEC 49 depends upon the different processing and data transfer rates along the two different data flow paths.
Another method of configuring processing blocks would be to utilize a parallel bus configuration, referring to FIG. 2. FIG. 2 illustrates a parallel bus configuration 80. The configuration includes processing blocks, such as DSP 82, first-in-first-out (FIFO) memory 84, DMA 86, random access memory (RAM) 88, CODEC 90 and mixer 92. The processing blocks are connected together by a common bus 94. Bus 94 generally includes an address bus and a data bus since the bus must interconnect several addresses.
Configuration 80 may be utilized to simulate different types of flow, as depicted in FIGS. 1A-1C. To simulate the processing steps illustrated in FIG. 1A data may be moved from DMA 86 to RAM 88 and then to mixer 92, all transactions passing through bus 94. After mixer 92 has finished processing the data, it may then be moved to CODEC 90 through bus 94. With further processing blocks connected to bus 94 the processing steps depicted in FIGS. 1B and 1C may be also be performed utilizing a single bus 94. However, there are downsides to utilizing a single bus 94 to move all the data from a number of different processing blocks.
Typically, in order to utilize a single bus, for example, bus 94, RAM 88 is required. In the configurations depicted in FIGS. 1A-1C data is passed from one processing block to another one word, or sample, at a time. Data also constantly flows from one processing block to another. However, in configuration 80 data is passed along from one processing block to another in large blocks of data. This is because bus 94 may only be utilized to carry information from one source to one destination at any one point in time.
A processing block may have to wait its turn in order to transfer its data to another processing block while another processing block is currently using bus 94. RAM 88, therefore, is required in order to accommodate the flow of data from DMA 86 to the other processing blocks. DMA 86 may output data to RAM 88 where it is stored until bus 94 is available to transfer the data from RAM 88 to another processing block. Similarly, processing blocks 82, 90 and 92 may also require storage elements in order to buffer information in between data transfers. Therefore DSP 82, CODEC 90 and mixer 92 would typically have RAM included within those processing blocks. Additionally, FIFO 84 may be utilized to store data for processing blocks that may not have internal storage elements.
The asynchronous characteristics of parallel configuration 80 lead to several drawbacks. Primarily, processing blocks may require additional storage elements in order to utilize bus 94. Each processing block also compete for bus time. The processing blocks may need to undergo an elaborate procedure for gaining access to bus 94 in order to complete its data transfer transaction. At the same time, collisions may occur when more than one processing block accesses bus 94 at the same time.
Since large blocks of information are transferred over bus 94 at any one data transfer a high frequency clock rate is necessary for bus 94. As can be appreciated by those skilled in art, a high frequency clock rate often times presents many design and implementation problems. And, generally only a fixed clock rate may typically be implemented on bus 94. Thus again the processing blocks must be synchronized to the clock rate of bus 94 in order to properly communicate among other processing blocks.
Thus, what is desired is a common bus that may be utilized by a number of processing blocks, but where the processing blocks are not necessarily fixed to the clock rate of a common bus. That is, the processing blocks independently operate according to their particular clock rates and still be able to transfer data from one processing block to another. Furthermore, a common bus that may be programmed to allow a myriad number of different combinations of processing blocks to communicate together is desired.
The present inventions provide apparatuses and methods for implementing a programmable bus. A programmable bus provides greater functionality and versatility through the ability to manage data transfers according to a number of sample rate clocks. The number of processing components connected to the programmable bus may be varied without a significant amount of physical alternations. Also, the number of data transfers for a given number of processing components may be modified and scheduled accordingly by reprogramming the programmable bus.
In one embodiment the programmable bus comprises a bus and a bus arbiter. The bus is coupled to the bus arbiter and a plurality of devices. The plurality of devices operate at different sample rate clocks. The bus arbiter schedules and conducts the transfer of data between the plurality of devices according to the sample rate clocks such that the plurality of devices send and receive data at appropriate times, corresponding to the sample rate clocks. Thus, the bus arbiter is programmable due to the ability to configure the bus arbiter to schedule and conduct the transfer of data between and among the plurality of devices.
In another embodiment, the programmable bus further includes a source address bus, a destination bus and a data bus. The bus arbiter asserts a source address on the source address bus to identify a source device of the plurality of devices for a particular data transfer. The bus arbiter asserts a destination address on the destination address bus to identify a destination device of the plurality of devices for the particular data transfer. And, the source device provides a piece of data on the data bus and the destination device receives the piece of data from the data bus. In yet another embodiment, each processing component may have multiple channels. The bus arbiter may then assert destination and source addresses that include channel addresses.
In another embodiment, the programmable bus includes a sample rate bus. The sample rate bus includes a plurality of sample rate clock lines. Each of the sample rate clock lines carries a sample rate clock. The plurality of devices are also coupled to the sample rate bus and operate at different sample rate clocks. The programmable bus conducts data transfers between and among the plurality of devices according to the sample rate clocks.
In yet another embodiment, the plurality of devices include interface circuitry to allow them to interface properly with the programmable bus. Each device includes an input buffer and an output buffer, the input buffer having a first and a second buffer, and the output buffer having a first and a second buffer. The programmable bus is further comprised of a buffer select line carrying a buffer select signal, such that the buffer select signal informs the plurality of devices whether to use the first or the second buffer of the input and output buffers for the transfer of data. Double buffering facilitates, in one embodiment, the transfer of data based upon different sample rate clocks.
These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following descriptions of the invention and a study of the several figures of the drawing.